Two ways to process more than one instruction at a time. Both run on the same clock below. Stages: IF fetch, ID decode, OF operand fetch, EX execute, WB write back.
The whole pipeline is copied. There are two of every stage, so two instructions enter together each cycle and travel side by side.
There is only one pipeline: one IF, one ID, one OF and one WB. Only the execute stage is split into five functional units. Slow operations (load 2 cycles, floating point 3 cycles) keep running in their unit while new instructions start in other units.
| (a) Multiple pipelines | (b) Multiple execution units | |
|---|---|---|
| What is copied | Every stage (IF, ID, OF, EX, WB) | Only the EX stage (ALU, ALU, LOAD, STORE, FP) |
| Instructions started per cycle | 2 (one per pipeline) | 1, but several can be executing at the same time |
| Where the parallelism is | Whole instructions run side by side | Slow operations overlap inside the execute stage |
| Hardware cost | High: a full pipeline per lane | Lower: one front end shared by all units |